The present invention relates to a semiconductor integrated circuit, and more particularly, to a circuit for inputting data to or outputting data from a synchronous dynamic random access memory (DRAM).
A semiconductor memory device used as a main memory of a computer system continually performs operations involving inputting and outputting data to and from memory cells. The data input and output speed of the semiconductor memory device can therefore be very important for determining the speed of operation of the computer system.
In a synchronous DRAM (SDRAM), internal circuits may be controlled in synchronization with an external clock signal generated by an external system. The SDRAM can be classified as either a single data rate SDRAM (SDR SDRAM) or a double data rate SDRAM (DDR SDRAM). In an SDR SDRAM, one piece of data is input or output during a single clock cycle in response to a rising edge of the external clock signal. In comparison, a DDR SDRAM, inputs or outputs two data items during a single clock cycle in response to rising and falling edges of the external clock signal.
As a result of it's higher speed, a DDR SDRAM includes a data input circuit for converting data that is serially input in response to the rising and falling edges of the external clock signal, into parallel data.
In an SDR SDRAM, input data is set up in synchronization with an external system clock signal, while in a DDR SDRAM, input data is set up in synchronization with a data strobe signal input through a data strobe pin. Also, in the SDR SDRAM, valid data is set up as one bit of data for each data pin during the period of an external system clock cycle, or in the DDR SDRAM, the valid data is set-up as one bit of data for each data pin during the period.
In an SDR SDRAM, the write latency is zero. This means that an SDRAM memory device writes in synchronization with the clock signal during which the data input is set up. However, in a DDR SDRAM, the SDRAM memory device writes in synchronization with the clock signal immediately after the clock period during which the data input is set up.
FIG. 1 is a circuit diagram of a data input circuit 100 of a conventional DDR SDRAM. This data input circuit 100 a data input buffer 101, a data strobe buffer 103, an internal strobe generation circuit 105, and a data setup circuit 107.
The data input buffer 101 buffers externally input data D.sub.EXT to generate internal data D.sub.INT. The data strobe buffer 103 buffers an externally input data strobe signal DS.sub.EXT to generate an initial data strobe signal DS.sub.INITIAL. The internal strobe generation circuit 105, delays the initial data strobe signal DS.sub.INITIAL for a predetermined period of time to generate an internal data strobe signal DS.sub.INT. The data setup circuit 107 receives the internal data D.sub.INT, the internal data strobe signal DS.sub.INT, and an internal clock signal ICLK, and outputs delayed data as parallel data D.sub.F and D.sub.S.
The signal P.sub.VCCH, is provided to the data setup circuit 107 to prevent the internal node of the chip from a misoperation and invalid latch phenomenon during power-up. P.sub.VCCH is maintained at a "low" state when the power voltage is under about 1.5 V, and is transited to a "high" voltage state when the power voltage rises above about 1.5 V.
The internal strobe generation circuit 105 is composed of a chain of several resistors 110, capacitors 115, and inverters 120, as shown in FIG. 2.
FIG. 3 is a circuit diagram of the data setup circuit 107 of the conventional data input circuit of FIG. 1. FIG. 4 is a timing diagram of a main terminal in the conventional data input circuit when the data burst length is 4.
The data setup circuit 107 of FIG. 3 includes a delay unit 301, multiple resistors 302, inverters 304, transistors 306, and transmission gates 310. First and second transmission gates 314 and 312 are discussed in detail below.
The delay unit 301, which delays internal data D.sub.INT for a period of time to generate delayed data D.sub.DELAYED, is itself composed of a multiplicity of inverter chains and capacitors. The delayed data D.sub.DELAYED, which is sequentially input, is controlled by the internal data strobe signal DS.sub.INT and an internal clock signal ICLK, as shown in FIG. 4. The controlled, delayed data is output as parallel data D.sub.F and D.sub.S. Signals DSDA and DSBI are related to the signal DS.sub.INT. The signal D.sub.INT is set up due to the signals DSBI and DSDA.
As shown in FIG. 4, an input command is generated during the activation of the first external clock cycle CLK1, i.e., the /WRITE signal is activated to low. The first and second data D.sub.1 and D.sub.2 are prepared to be propagated in synchronization with the second external clock cycle CLK2, and output as D.sub.F and D.sub.S in synchronization with the third external clock cycle CLK3. Third and fourth data D.sub.3 and D.sub.4 are set up in synchronization with the third external clock cycle CLK3, and output as D.sub.F and D.sub.S in synchronization with the fourth external clock cycle CLK4.
Here, the internal clock signal ICLK is generated in synchronization with an external system clock signal CLK. The internal clock ICLK goes "high" in response to the rising edge of the external clock signal CLK. The internal clock signal then goes "low" after a predetermined time period.
In the conventional data input circuit of FIGS. 1 through 3, the data setup circuit 107 includes a delay unit 301, and the internal strobe generation circuit 105 includes a delay circuit composed of a chain of inverters and capacitors.
In the DDR SDRAM, a post-amble interval, i.e., the interval from the point that the signal DS.sub.EXT goes "low" for receiving the last D.sub.INT to the point that the signal DS.sub.EXT goes to a tri-state, is a 1/2 clock cycle of the external clock signal CLK. Thus, when an interval of half the clock cycle of the external clock signal CLK has passed after a time point T.sub.4, indicating the input of the fourth data D.sub.4, a data strobe signal DS.sub.EXT may move to a high impedance state. The time T.sub.1, indicating the input of the first data, is a data set up time period t.sub.DQSS from the rising edge of the external clock signal to the low transition point of the signal DS.sub.EXT.
However, because the internal strobe generation circuit 105 includes a delay circuit, the internal clock signal ICLK becomes high at a point in time at which the internal data strobe signal DS.sub.INT is in an unknown state. The transmission gates 312 and 314 are turned off to prevent the transfer of invalid data to nodes N315 and N317. This can prevent the output of an unknown state of the two parallel data D.sub.F and D.sub.S.
Unless the conventional data input circuit has the internal strobe generation circuit 105 and the delay unit 301, as shown in FIG. 5, the internal data strobe signal DS.sub.INT is in the unknown state before the fourth clock cycle CLK4 is high. Thus, the two parallel data D.sub.F and D.sub.S generated by the fourth clock cycle CLK4 of the CLK signal are output in the unknown state instead of the third and fourth input data D.sub.3 and D.sub.4. In particular, FIG. 5 shows the problems associated with a write modc on low frequency.
Due to the internal strobe generation circuit 105 of the conventional data input circuit and the delay time due to the delay unit 301 of the data setup circuit 107, the delay time may vary according to the temperature or the operational voltage. Therefore, the data input setup margin may be deficient, as shown in both FIGS. 5 and 6.